紀要論文

Design of a Pipelined CPU including FPU based on SIMD Architecture

jpn

18810667

https://doi.org/10.15002/00010514

法政大学大学院情報科学研究科

9

21

26

2014-03

Version of Record

Abstract-lncresismg demands for data processing capabilities require CPU not only with enormous integer computational capacities but also with sufficient speed to handle complicated floating point operation [4]. In this paper, according to the features of SIMD, we design a set instructions which includes integer and floating-point double data instructions. According to these set instructions, we design a pipelined CPU including the FPU based on the SIMD architecture to achieve high speed in handling integer and floating computing tasks. The CPU architecture consists of two SIMD processing modules which have their own registers and a shared memory. This allows highly and flexible computation of complicated integer and floating stream data tasks, which are difficult to deal with using a conventional CPU architecture. The goal of this research is to design a processor which can process the integer and floating point based on SIMD architecture.

Article

AA12222297