学位論文

ノイズシェーピング構成とミスマッチシェーパーを用いた自己校正型パイプラインADCに関する研究

A pipelined ADC using background calibration with mismatch shaper and noise shaping architecture

jpn

2012-03-24

Not Applicable (or Unknown)

2012-03-24

修士(工学)

工学研究科電気工学専攻; 指導教授: 安田彰

A novel background calibration technique for capacitor mismatches is proposed in this paper. The capacitor mismatch is one of the non-ideal factors in the pipelined ADC. This non-ideal factor deteriorates Signal to Noise Ratio (SNR) and Total Harmonic Distortion (THD). The conventional calibration method utilized both Noise Shaping Dynamic Element Matching (NSDEM) and a high-pass delta-sigma modulation. Recently, the architecture which is based on two step pipelined ADC and uses delayed quantization error to implement noise shaping function is studied. In this paper, we proposed a novel calibration method which uses NSDEM and this architecture. As a result, the SNR of the overall ADC can be improved.

Thesis